In a processor supporting virtual memory, the virtual address provided by the CPU has to be translated to a physical address. This is typically accomplished by a Memory management unit (MMU). The MMU typically uses a μTLB (micro-translation look-aside buffer) as a cache of the page translation entries stored in the MMU. Every virtual address requested by CPU needs to be translated to the physical address by the μTLB/MMU for memory access. This is typically performed on page boundaries.
The virtual address to physical address translation happens at the page boundaries (the lowest granularity of page size being 4K). If an access address to be translated is a hit in μTLB, translation takes place in a single cycle. But if the access address is a miss in μTLB, the translation data for that page has to be requested from the MMU. This translation data fetch may take tens to hundreds of cycles depending on the page translation and page table walk latency in the MMU.
The MMU/μTLB typically also provides permission information for the translations. This permission information is stored in the L1I cache because for L1I hits, the permission information is needed to service the request.
If every virtual address is looked up through the μTLB, and if the μTLB entries can be invalidated by the MMU, then there will probably be a long μTLB miss latency. This will also result in increased dynamic power consumption if the μTLB is implemented in SRAM memory.